1. Field of the Invention
The present invention relates to a memory cell of a static RAM and an array of such memory cells.
2. Description of the Prior Art
In a static M (hereinafter referred to as SRAM) having a storage capacity of 256 kilobits to 4 megabits, it has been customary heretofore that two driver transistors are disposed on one side of each word line constituting a word transistor.
However, in any SRAM of a storage capacity exceeding 16 megabits, memory cells each using a thin film transistor (TFT) as a load are principally employed, and therefore it is necessary to form an adequate pattern adapted for such a structure.
For achieving the above requirement, there is proposed an SRAM cell of an exemplary pattern illustrated in FIG. 1.
This diagram merely shows word lines 1, 2 composed of a first-layer polycrystal silicon film, and gates 3, 4 of driver transistors out of entire component parts constituting an SRAM cell 5.
The two word lines 1, 2 are disposed in parallel with each other for one memory cell 5, and the gates 3, 4 of driver transistors are disposed between the two word lines 1, 2 in parallel thereto.
In the SRAM cell of such constitution, there exists a drawback that the area of the cell is relatively large due to the presence of two word lines disposed in each cell.
Furthermore, in an SRAM of a storage capacity ranging from 256 kilobits to 4 megabits, two driver transistors are disposed on one side of a single word line constituting a word transistor. Meanwhile in an SRAM of a storage capacity exceeding 16 megabits, there are principally employed memory cells each using a thin film transistor as a load, so that an adequate pattern adapted for such a structure becomes necessary. In one conventional SRAM cell array, as shown in FIG. 2, memory cells 7 are arranged horizontally and vertically in a manner to respectively have a positional deviation corresponding to the length of one cell, and each column of the memory cells 7 arrayed in parallel with bit lines has one bit-line pair.